HPC. SC15.

El sector HPC tiene dos principales ferias anuales, una en Europa y la otra en EEUU.

Como todos los noviembres, ahora mismo (15-20 de  noviembre) se está desarrollando la feria de EEUU.

En breve se publicarán las novedades en la actualización del ranking del TOP500, también bianuales y coincidentes con las ferias.

De la página web extraigo las siguientes páginas que he encontrado interesantes.

Emerging technologies.

In the Emerging Technologies track of the Technical Program, SC15 will examine innovative solutions that may significantly change and extend the world of HPC in the next five to fifteen years. Consisting of panel sessions and competitively selected exhibits, Emerging Technologies will showcase technologies that are innovative but not yet available from industry as products. Technologies such as reconfigurable computing, new SoC designs, 3D memory technologies, non-volatile memory, alternative programming languages, and novel cooling techniques may offer medium-term benefits, while new device technologies such as carbon nanotubes, photonic interconnects, chip-level optical interconnects, quantum computing and next generation optical computers, offer potentially paradigm-changing benefits over the longer term.

Y dentro de esta apartado extraemos el siguiente artículo o presentación.

EMULATING FUTURE HPC SOC ARCHITECTURES

Current HPC ecosystems rely upon Commercial Off-the-Shelf (COTS) building blocks to enable cost-effective design by sharing costs across a larger ecosystem. Modern HPC nodes use commodity chipsets and processor chips integrated together on custom motherboards. Commodity HPC is heading into a new era where the chip acts as the “silicon motherboard” that interconnects commodity Intellectual Property (IP) circuit building blocks to create a complete integrated System-on-a-Chip (SoC). These SoC designs have the potential for higher performance at better power efficiency than current COTS solutions. We will showcase how the advanced tools provided by the Co-Design for Exascale (CoDEx) project running on a cloud-based FPGA system can provide powerful insights into future SoC architectures tailored to the needs of HPC. The large-scale emulation environment shown here will demonstrate how we are building the tools needed to evaluate new and novel architectures at speeds fast enough to evaluate whole application performance.

Terms and conditions: 1. Any commenter of this blog agrees to transfer the copy right of his comments to the blogger. 2. RSS readers and / or aggregators that captures the content of this blog (posts or comments) are forbidden. These actions will be subject to the DMCA notice-and-takedown rules and will be legally pursued by the proprietor of the blog.

Introduce tus datos o haz clic en un icono para iniciar sesión:

Logo de WordPress.com

Estás comentando usando tu cuenta de WordPress.com. Cerrar sesión / Cambiar )

Imagen de Twitter

Estás comentando usando tu cuenta de Twitter. Cerrar sesión / Cambiar )

Foto de Facebook

Estás comentando usando tu cuenta de Facebook. Cerrar sesión / Cambiar )

Google+ photo

Estás comentando usando tu cuenta de Google+. Cerrar sesión / Cambiar )

Conectando a %s


A %d blogueros les gusta esto: