Otra serie de artículos relacionados, bastante indirectamente, con los **sistemas RH**. Si una red de interconexión punto a punto se puede modelar por un grafo, una red de interconexión de tipo bus se puede modelar por hipergrafos, en cuyo caso los vértices siguen siendo vértices, pero los hiperarcos pueden /suelen contener más de dos vértices. Aparentemente se publicó algo sobre este tipo de redes de interconexión en los 90, y posteriormente se dejó de publicar (aunque he encontrado un artículo de 2009 en el que hablan sobre ellas).

Hay diferencias entre las redes de interconexión de tipo bus y los sistemas RH.

En una red punto a punto (como en principio lo son los sistemas RH), físicamente las comunicaciones se hacen de nodo a nodo (de router a router, de conmutador a conmutador); en una red multibus, las comunicaciones se hacen de nodo a todos los otros nodos que comparten un mismo bus.

Otra diferencia es que las primeras utilizan la técnica de **conmutación de circuitos** (en cada bus) y los segundos están más pensados (hasta ahora) en modo **conmutación de paquetes**. Al extremo, si contemplamos arcos que contengan todos los vértices del dígrafo, entiendo que estamos contemplando sistemas similares a los RH. Tema a estudiar.

**0. 1986.**

** Analysis of Multiple-Bus Interconnection Networks***

T. N. MUDGE, J. I? HAYES, G. D. BUZZARD, AND D. C. WINSOR

*Advanced Computer Architecture Laboratory, Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Michigan 48109-I 109 Received February 4, 1985 The performance of multiple-bus interconnection networks for multiprocessor systems is analyzed, taking into account conflict arising from memory and bus interference. A discrete stochastic model of bandwidth is presented for systems in which each memory is connected either to all the buses or to a subset of the available buses. The effects of the assumptions made concerning independence among requests for different memories (spatial independence) and resubmission of blocked requests (temporal independence) are investigated systematically. The basic bandwidth model is extended to account for spatial dependence, and compared to previously proposed models. Finally, the various analytic models are shown to be in close agreement with simulation results. *

**1.1992.**

**Larry Finkelstein y Gene Cooperman.**

*PERMUTATION ROUTING VIA CAYLEY GRAPHS WITH AN EXAMPLE FOR BUS INTERCONNECTION NETWORKS*.

**ABSTRACT**

*Cayley graphs have been used extensively to design interconnec- tion networks and provide a natural setting for studying point-to-point routing (1, 2, 3, 5, 6, 7, 12). The extension of these techniques to the more important problem of permutation routing on interconnection networks presents funda- mental problems. This is due to the potentially explosive growth in both the size of the graph and the number of generating permutations, referred to as one-step permutation routes, used to define the underlying graph. This pa- per describes a technique for moderating that growth so that the techniques in (8) can be applied for finding optimal permutation routes. In a particularly striking example, a bus interconnection architecture involving 1.0× 1017 per- mutations (nodes of the Cayley graph) is reduced to a computation on a graph with only 3,950 nodes. Further, it is shown how many of the 58,624 generators (directed edges labelled by one-step permutation routes) at each node of the graph may be eliminated as locally redundant.*

*2. 1996. *

*Bus interconnection networks*

**3. 1999.**

*Broadcasting in bus interconnection networks.*

A. Ferreira, A. Goldman, S.W. Song.

**4. 2009.**

*Scalable arbitration of partitioned bus interconnection networks in 3D-IC systems.*

*In this paper, we describe a scalable interconnection network architecture intended for very large multicore processors implemented on stacked chip 3D integrated circuits (3D-IC). These networks provide fully interconnected, low latency, single hop performance with wiring complexity that scales linearly with the size of the network. The enabling technology for these networks is a novel, fully distributed arbitration and control algorithm that operates solely at the edges of the network without the need for any routers within the network core. This paper is focused on a description of that algorithm. We present simulation results for average, worst-case, and per-node latencies showing that our arbitration algorithm performs efficiently, scales for a wide range of partition sizes, and effectively manages highly non-uniform traffic patterns.*

**P.s.** Por el camino me he encontrado este artículo en el que sugieren una nueva forma de ver / modelar las redes de interconexión (de tipo NoC): como sistemas termodinámicos.

**Toward a science for future NoC design**

*Traditionally, the design space exploration for systems-on-chip has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip and their performance continue to increase, the design of the communication architecture plays a major role in defining the area, performance, and energy consumption of the overall system. From a technology point of view, this paradigm shift is meant to mitigate the problem of interconnects, keep the design complexity under control, and reduce costs. Since neither point-to-point, nor bus-based communication scale well in terms of power and performance figures, the network-on-chip architecture has been suggested as a promising solution for future multicore systems.*

*In this talk, we plan to address the concept of “network” in multiprocessor systems-on-chip and identify specific design principles and optimization techniques that are relevant to our research community. More precisely, we plan to discuss fundamental mathematical techniques that can be used to design, control, and optimize such networks in a rigorous manner at nanoscale. At the same time, we plan to also highlight alternatives to the conventional paradigm of network design. This new vision is based on rigorous developments in the field of statistical physics and information theory that allow us to model the network as a thermodynamical system. The hope is that this new modeling paradigm can enable not only capturing the intrinsic interactions among various network components, but also developing powerful techniques for predicting and optimizing the on-chip network behavior.*

Ver también:

*The Chip Is the Network: Toward a Science of Network-on-Chip Design.*

Radu Marculescu1 and Paul Bogdan2 1 Department of Electrical and Computer Engineering, Carnegie Mellon University,

**Abstract**

*In this survey, we address the concept of network in three different contexts representing the deterministic, probabilistic, and statistical physics-inspired design paradigms. More precisely, we start by considering the natural representation of networks as graphs and discuss the main deterministic approaches to Network-on-Chip (NoC) design. Next, we introduce a probabilistic framework for network representation and optimization and present a few major approaches for NoC design proposed to date. Last but not least, we model the network as a thermodynamic system and discuss a statistical physics-based approach to characterize the network traffic. This formalism allows us to address the network concept in the most general context, point out the main limitations of the proposed solutions, and suggest a few open-ended problems.*

…

*Along these lines, Bogdan and Marculescu [32] propose a paradigm shift in NoC design based on the analogy between the network and thermodynamic gas behaviors. This becomes possible based on the observation that each buffer of the NoC, at any point in time, can be characterized by a particular energy level. More precisely, the main idea is that packets in the network move from one node to another in a manner that is similar to particles moving in a Bose gas and migrating between various energy levels as a result of temperature variations*

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